The Intermediate Communications Array Processor is a MIMD grid of high performance processors that are used for intermediate level image understanding tasks such as perceptual grouping.
Each processor (IPE) is capable of performing very complex functions independently of the other processors.
It is also able to cooperate on the decomposition of even more complex tasks by communicating with its peers.
Each IPE has its own memory.
It communicates to its immediate neighbors using shared memory and high speed channels.
It communicates to its other peers using high speed channels.
It is able to obtain data at high rate from the SIMD layer of the IUA through a shared memory (CISM).
ICAP Processing Element (IPE)
The IUA uses the Texas Instruments TMS320C40 Digital Signal Processor as the processing element (IPE) for the MIMD layer of the IUA.
The following quote is from the Texas Instruments TMS320C4x User's Guide (1991).
``Texas Instruments' TMS320C4x generation of floating-point processors are designed specifically to meet the needs of parallel processing and other real-time embedded applications.
... designers are able to fully utilize the immense performance of 275 MOPS (millions of operations per second) and 320 Mbytes per second throughput made available by the TMS320C4x generation.''
The TMS320C40 was chosen to be the IUA ICAP IPE because it satisfied the following requirements:
Each IPE operates at 40 MHz.
- Full capability processor with
- Large address space
- Fast floating point operations
- Fast interrupt processing
- Requires minimal board space (minimal glue logic)
- Capability for inter-processor communications to a large number of peer processors
IPE Private Memory (IPM)
The IPM consists of 4 Mbytes per IPE of private, local high speed SRAM.
This memory is used to hold both program and local data.
The IPE has access to a portion of the ICAP Shared Memory (ISM) that is in the quadnode.
This memory is used for the storage of global information such as a distributed image event database.
The IPEs communicate using the TMS320C40 communication ports.
There are six such bi-directional ports on each IPE, 24 on a quadnode.
Each communications channel is capable of 20 Mbytes/sec.
Each channel can be simultaneously active.
Two of the channels on each node are used to connect the four IPEs in a quadnode together in a ring network.
Fifteen of the remaining sixteen channels in the quadnode are used to connect to the other quadnodes in the IUA.
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