IUA Glossary

Abstract Machine
The abstract machine is the software interface between the CP and the uC. The abstract machine is designed to be the target of a compiler. It provides an intermediate form between the type of computer to which most compilers are targeted and the much different form of the CAAPP. The microcode, running in the uC, emulates the abstract machine and generates the CAAPP instructions. It is possible to have several different abstract machine definitions that define different sets of abstract machine instructions.
Abstract Machine Instruction
An Abstract Machine Instruction is the sequence of one or more consecutive pFIFO words which is interpreted by the microcode as an instruction for the Abstract Machine.
Array Control Unit. The ACU controls the overall behavior of the IUA. It consists of the user-programmable CP and the uC. The CP generates instructions to the uC, which in turn generates primitive CAAPP instructions. Other functions may be performed by the CP as well.
Auxillary Processor. An AP is a processor on the IUA VMEbus that is not otherwise defined in this document. An AP may perform high-level knowledge-based vision operations or operations unrelated to vision processing. Each AP runs a real-time operating system (VxWorks) and may support other I/O devices.
Backing-Store Memory. BSM is a generic term applied to all off- CAAPP-chip memory directly accessible by the CAAPP. Currently, this memory consists of the HCSM and CISM. It is used primarily for the storing of the plane variables in a user's primary CP task that controls the CAAPP. Each CAAPP PE has access to its own small portion of BSM.
Content Addressable Array Parallel Processor. The CAAPP is an array of bit-serial SIMD processors arranged in a rectangular grid and designed to do low-level image understanding tasks using a single processor per pixel paradigm. The CAAPP was originally designed by Charles Weems as his Ph.D. dissertation.
Count response and status FIFO. The cFIFO is a hardware queue that captures feedback from the CAAPP and ICAP levels of the IUA and returns it to the CP. Generally, this queue is used to return histogram counts from the CAAPP to the user's CP program.
CAAPP-ICAP Shared Memory. CISM is a block of memory that the CAAPP and ICAP layers share and use for communication between the layers. Each CAAPP PE has access to its own small part of CISM. Each ICAP PE has access to the CISM of 256 CAAPP PEs.
Common Object File Format. COFF is the object file format produced by the TI TMS320C40 C compiler.
Control Processor. The CP is a general purpose, programmable processor. It issues commands to the uC and can also read and write the shared memories visible on the VMEbus, such as ISM and HCSM.
DIS/GFX Library
This device-independent graphics display library is a part of KBVision. The IUA implementation of KBVision's ISR Database includes a port of this library to support display of database objects.
Host-CAAPP Shared Memory. HCSM is a block of memory accessible by both the CAAPP and the IDTS. HCSM supports image I/O to and from the IUA; the IDTS loads image data into this memory for CAAPP processing, and reads from it image data to be output. Like CISM, each CAAPP PE has access to its own small portion of this memory.
In the context of the IUA, a host is any computer connected to the IUA over ethernet that provides a connection between the user and the IUA. A Host provides an interface consisting of displays and a keyboard, and the corresponding monitor and control software. The host may also provide the IUA with access to a filesystem and general purpose I/O (text and non-real-time graphics). In some applications (e.g., UGV) the IUA may run without a host.
Intermediate Communications Array Processor. The ICAP is a network of independent processors primarily used for intermediate-level symbolic operations.
Image Data Transfer System. The IDTS is an I/O sub-system designed to provide high bandwidth transfers of images to and from the IUA. For example, the IDTS can move data among a series of DataCube image acquisition and display boards, and HCSM.
Instruction FIFO. The iFIFO is a hardware queue that buffers CAAPP instructions sent by the uC to the CAAPP.
An image is a digital representation of two dimensional sensory input.
ICAP Processing Element. An IPE is one ICAP layer processing element (i.e., one TMS320C40 processor chip and associated hardware).
ICAP Private Memory. Each IPE has a block of fast-access private (non-shared) memory, IPM, in which it stores both code and private data.
ICAP Shared Memory. ISM is a block of memory that the IPEs on a quadnode share. The ISR database, among other things, resides in ISM.
ISR Database
Intermediate Symbolic Representation Database. The ISR Database is a database containing tokens that represent events in an image, from primitive events such as lines and regions to abstract events such as roads and trees. Tokens may also represent object models and schemas for matching. The database information is distributed among the quadnodes. The ISR was originally developed at the University of Massachusetts.
Image Understanding Architecture. The IUA is a massively parallel, three level, computer architecture, originally developed at the University of Massachusetts, and designed to provide superior performance on image understanding tasks.
Load File
A Load File is a disk file that contains the information a loader uses to load code (and static data) into a processor's memory. Load files typically result from running a linker on a set of object files and libraries. A process running on an IPE is loaded from a single load file, while a process running on the CP may be loaded from a number of load files.
A loader is a program that loads code and static data into a processor's memory. There are special loaders for each type of processor in the IUA except CAAPP PEs, whose instructions come from the ACU.
Micro-Controller. The uC consists of the uE and the PP. The uC accepts commands from the CP and interprets the commands as subroutine calls to internal micro-coded routines that implement abstract machine instructions. The uC also accepts runtime parameters for the subroutine calls from the CP.
Micro-Engine. The uE runs the micro-coded routines that implement the abstract machine. The uE puts CAAPP instructions into the iFIFO, which connects to the PP. The uE can be programmed to synchronize its execution with the CP or with logical conditions defined on the status lines received from the CAAPP and ICAP arrays.
CAAPP Processing Element. One of the bit-serial processors in the CAAPP.
Parameter FIFO. The pFIFO is a hardware queue that buffers abstract machine instructions sent by the CP to the uC.
A plane is a rectangular grid of elements with an implied mapping from one element to one PE. (When a plane is larger than the CAAPP, tiling is used to implement a virtual CAAPP). Currently, these elements are restricted to be scalar values. A plane has two dimensions -- a number of rows and a number of columns. The element in the upper left hand corner of a plane has a row index of 0 and a column index of 0. Planes are typically used to represent images although they may be used to represent any two dimensional grid of elements. Note that a plane is a parallel data type. Unlike the array construct familiar in sequential programs, a plane does not support sequential operations such as indexing.
A process is an execution context containing memory and other resources. It may have many threads of control which we call tasks.
Post-Processor. The PP accepts CAAPP instructions from the iFIFO and issues them to the CAAPP array. It guarantees that successive backing store instructions do not interfere with each other. The PP accepts count response and status information from the CAAPP array and places the information into the cFIFO. It also generates CAAPP refresh instructions.
A quadnode is a partition of the IUA hardware that contains four IPEs, the CAAPP PEs whose backing store memory the IPEs can access, the backing store memory for those PEs ( CISM and HCSM), memory shared among the four IPEs ( ISM), and other memory and hardware. The IUA consists of a number of identical quadnodes, the ACU, and other hardware.
Remote Procedure Call. RPC is a programming model in which tasks communicate in a client-server relationship using what look like normal procedure calls. When the client task calls an RPC procedure, the underlying software creates and sends a message to the server task. The software in the server task then interprets the message, services the request, and places the return values, if any, into another message which is sent back to the client. In typical RPC communications, the client task waits for a reply from the server before proceeding.
Single Instruction, Multiple Data. SIMD is one of various ways of implementing parallelism in computer architectures. In this form, a large group of simple processors all perform the same task at the same time, each with different data. Low level image understanding tasks generally map very well to SIMD architectures because images consist of rectangular grids of pixels that are all processed the same way.
Symbolic Processing Array. The SPA consists of those processors that are part of, or are connected to, the IUA and that perform knowledge-based image understanding tasks. In the original IUA architecture, the SPA was the top level array of processors designed to specifically execute schema systems. In the current IUA, any processor that performs high-level vision tasks is considered to be part of the SPA even if it also performs non-SPA tasks as well.
SPOX is a small operating system, from Spectron Inc., for high-end digital signal processors such as Texas Instruments' TMS320C40. It provides device-independent I/O, interrupt management, multi-tasking support, and other services. It is organized as two sets of libraries: SPOX-OS, providing system functions such as I/O, timer services, and preemptive scheduling, and SPOX-AL, defining a number of abstract types such as arrays, vectors, and matrices. The user links these libraries with their code to create a load file for a multi-tasking ICAP process.
The kernel portion of SPOX.
The application library portion of SPOX.
A task is a computation with its own stack and program counter, but that shares memory with other tasks within a processor. We use the term task, rather than the more common term thread, for consistency with the documentation of SPOX and VxWorks.
A tile is a subpart of a plane. A plane is partitioned into multiple tiles all of the same size. The number of tiles depends on the physical size of the CAAPP as each tile is exactly the same size as the physical CAAPP. We use the term tile when discussing how a plane that is larger than the CAAPP is utilized by the CAAPP. When a plane contains more than one tile, then each physical PE is mapped to more than one element in the plane.
Unmanned Ground Vehicle. UGV is a project sponsored by DARPA to provide a semi-automous, reconnaissance vehicle for the Armed Services. The project is being used to drive research in many areas including Image Understanding.
The VMEbus is an electrical bus over which multiple processors communicate using a standard protocol. The APs and CP communicate over the VMEbus and use it to read and write quadnode data (e.g., ISM and HCSM data). The IEEE/ANSI standard 1014 document, VMEbus Specification Revision C.1, October 1985. (Also known as IEC 821 BUS and IEEE P1014/D1.2.), defines the VMEbus protocol.
VxWorks is a real-time non-virtual operating system, based on Unix, from Wind River Systems, Inc. The CP and the APs run VxWorks.
Xlib is a library of functions for displaying text and graphics and receiving input through (possibly remote) servers attached to displays and input devices. This library is part of the X Windowing System, a product distributed by the X Consortium.

IUA Outline