Texas Instruments' TMS320C40 DSP Processor

• Six communication ports for high speed interprocessor communication. Communication port key features include:
  • 20-Mbytes/sec asynchronous transfer rate at each port for maximum data throughput
  • Direct (glueless) processor-to-processor communication for ease of use
  • Bidirectional transfers for maximum communication flexibility
• Six-channel DMA coprocessor for concurrent I/O and CPU operation, thereby maximizing sustained CPU performance by alleviating the CPU of burdensome I/O. DMA coprocessor key features include:
  • Concurrent data transfers and CPU operation for sustained CPU performance
  • Self-programming (autoinitialize) capability for each channel, thereby not requiring the CPU for initializing, maximizing sustained CPU performance
  • Data transfers to and from anywhere in the processor's memory map for maximum flexibility.
• High-performance DSP CPU capable of 275 MOPS and 320 Mbytes/sec. CPU key features include:
  • Eleven operations per cycle throughput, resulting in massive computing parallelism and sustained CPU performance
  • 40-ns and 50-ns instruction cycle times
  • 40/32-bit single-cycle floating point/integer multiplier for high performance in computationally intensive algorithms
  • Single-cycle IEEE floating-point conversion for efficient interface to IEEE-compatible processors
  • Hardware divide and inverse square root support for high performance
  • Byte and half-word manipulation capabilities for fast data (un)packing
  • Source code compatible with TMS320C3x generation for easy upward and downward mobility
  • Support for linear, circular, and bit-reversed addressing for high performance
  • Single-cycle branches, calls,, and returns for fast program control
  • Single-cycle barrel shifter for 0-31 single-cycle right or left shifts for fast bit manipulation
  • Relocatable reset and interrupt vectors for easy integration into parallel processing systems
• Two identical external data and address buses supporting shared memory systems and high data rate, single-cycle transfers. Key features include:
  • High port data-transfer rate of 100 Mbytes/sec
  • 16-Gbyte continuous program/data/peripheral address space for maximum design flexibility
  • Status pins that signal type of memory access requested for fast, intelligent bus arbitration in shared memory systems
  • Separate address, data, and control-enable pins for high-speed bus arbitration
  • Four sets of memory-control signals support different speed memories in hardware, enabling efficient use of low- and high-speed memories
• On-chip analysis module supporting efficient, state of the art parallel processing debug. Key features include:
  • Separate breakpoint comparators for program, data, and DMA accesses, providing onchip hardware breakpoint capabilities for fast debug and development
  • Discontinuity stack for hardware trace, facilitating fast debug and development
  • Event counter for accurate benchmarking and profiling
  • JTAG interface for standard system connection

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